1. Field of the Invention
The present invention relates to computing systems, and more particularly to testing PCI Express devices and/or other networking devices.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®, or the extension of PCI known as PCI-X. More recently, PCI Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
Host systems are used in various network applications, including TCP/IP networks, storage area networks (“SANs”), and various types of external device attachment. In SANs, plural storage devices are made available to various host computing systems. Data is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification). The connectivity between a host system and networks or external devices is provided by host bus adapters (“HBAs”), which plug into the host system. HBAs may attach to the host system via a standard interface such as PCI Express.
PCI Express HBAs receive serial data streams (bit streams), align the serial data and then convert it into parallel data for processing. PCI Express HBAs operate as transmitting devices as well as receiving devices.
PCI Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that uses discrete logical layers to process inbound and outbound information. The logical layers are a Transaction Layer, a Data Link Layer (“DLL”) and a Physical Layer (“PHY”). PCI-Express uses separate links to transmit and receive information.
PCI-Express uses a packet-based protocol to exchange information between Transaction layers. Transactions are carried out using Requests and Completions. The Transaction Layer assembles and disassembles Transaction Layer Packets (“TLPs”). TLPs are used to communicate transactions, such as read and write and other type of events.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
PCI Express packets received on a link may come with little or no inter-packet gap. The packets need to be efficiently pipelined and processed to sustain high data throughput rates.
PCI Express devices in general and HBAs in particular are tested based on transactions using a bus functional model (“BFM”). The transactions need to be generated with minimum gap to test the logic. This is difficult to achieve in the PCI Express environment because of the overall PCI Express architecture as described below.
In the PCI Express environment, PCI Express port logic uses a store/forward buffer to move packets that are received from a host to a PCI Express Transaction Handler (“PTH”). PTH is a part of the logic that needs to be tested to handle different spacing between the TLPs. The store/forward buffer is used to store and validate entire packets before they are sent to the PTH. It becomes difficult to control test cases and to simulate internal boundary conditions in the PTH, especially when large packets follow small packets, since the large packets take longer to be released from the store/forward buffer.
Also, often TLPs are mixed with dynamic data link layer packets (“DLLPs”). When the DLLPs are stripped from the data path in the data link layer, the transactions that are left in the data path have bigger gaps. Hence, the PCI Express logic is not able to test all combinations of gaps between these packets efficiently.
It is noteworthy that the foregoing challenge for testing logic is also applicable to other input/output interfaces, similar to PCI Express devices.
Therefore, there is a need for a method and system for testing logic for a network device/PCI Express device.